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profet ? bts 726 l1 semiconductor group 1 06.96 smart two channel highside power switch features overload protection current limitation short-circuit protection thermal shutdown overvoltage protection (including load dump) fast demagnetization of inductive loads reverse battery protection 1 ) undervoltage and overvoltage shutdown with auto-restart and hysteresis open drain diagnostic output open load detection in on-state cmos compatible input loss of ground and loss of v bb protection e lectro s tatic d ischarge ( esd ) protection application m c compatible power switch with diagnostic feedback for 12 v and 24 v dc grounded loads all types of resistive, inductive and capacitive loads replaces electromechanical relays and discrete circuits general description n channel vertical power fet with charge pump, ground referenced cmos compatible input and diagnostic feedback, monolithically integrated in smart sipmos a technology. fully protected by embedded protection functions. pin definitions and functions pin symbol function 1,10, 11,12, 15,16, 19,20 v bb positive power supply voltage . design the wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance 3 in1 input 1,2 , activates channel 1,2 in case of 7 in2 logic high signal 17,18 out1 output 1,2 , protected high-side power output 13,14 out2 of channel 1,2. design the wiring for the max. short circuit current 4 st1 diagnostic feedback 1,2 of channel 1,2, 8 st2 open drain, low on failure 2 gnd1 ground 1 of chip 1 (channel 1) 6 gnd2 ground 2 of chip 2 (channel 2) 5,9 n.c. not connected 1 ) with external current limit (e.g. resistor r gnd =150 w ) in gnd connection, resistor in series with st connection, reverse load current limited by connected load. product summary overvoltage protection v bb(az) 43 v operating voltage v bb(on) 5.0 ... 34 v active channels: one two parallel on-state resistance r on 60 30 m w nominal load current i l(nom) 4.0 6.0 a current limitation i l(scr) 16 16 a pin configuration (top view) v bb 1 20 v bb gnd1 2 19 v bb in1 3 18 out1 st1 4 17 out1 n.c. 5 16 v bb gnd2 6 15 v bb in2 7 14 out2 st2 8 13 out2 n.c. 9 12 v bb v bb 10 11 v bb
bts 726 l1 semiconductor group 2 block diagram two channels; open load detection in on state; in1 st1 esd logic voltage sensor voltage source open load detection charge pump level shifter temperature sensor rectifier limit for unclamped ind. loads gate protection current limit 3 4 v logic overvoltage protection gnd1 r o1 signal gnd gnd1 1 chip 1 chip 1 in2 st2 profet a 7 8 6 gnd2 r o2 leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20 signal gnd gnd2 chip 2 chip 2 + v bb out1 leadframe 17,18 load gnd load + v bb out2 leadframe 13,14 load gnd load logic and protection circuit of chip 2 (equivalent to chip 1) maximum ratings at t j = 25c unless otherwise specified parameter symbol values unit supply voltage (overvoltage protection see page 4) v bb 43 v suppl y volta g e for full short circuit protection t j,start = -40 ...+150c v bb 34 v
bts 726 l1 maximum ratings at t j = 25c unless otherwise specified parameter symbol values unit semiconductor group 3 load current (short-circuit current, see page 5) i l self-limited a load dump protection 2 ) v loaddump = u a + v s , u a = 13.5 v r i 3 ) = 2 w , t d = 200 ms; in = low or hi g h, each channel loaded with r l = 3.4 w , v load dump 4 ) 60 v operating temperature range storage temperature range t j t stg -40 ...+150 -55 ...+150 c power dissipation (dc) 5 t a = 25c: (all channels active) t a = 85c: p tot 3.7 1.9 w inductive load switch-off ener gy dissipation, sin g le pulse v bb = 12v, t j,start = 150c 5) , i l = 4.0 a, z l = 50 mh, 0 w one channel: i l = 6.0 a, z l = 42 mh, 0 w two parallel channels: see diagrams on page 9 and page 10 e as 0.5 1.0 j electrostatic dischar g e capabilit y ( esd ) (human body model) v esd 1.0 kv input voltage (dc) v in -10 ... +16 v current through input pin (dc) current through status pin (dc) see internal circuit diagram page 8 i in i st 2.0 5.0 ma thermal resistance junction - soldering point 5),6) each channel: r thjs 12 k/w junction - ambient 5) one channel active: all channels active: r thja 41 34 2 ) supply voltages higher than v bb(az) require an external current limit for the gnd and status pins, e.g. with a 150 w resistor in the gnd connection and a 15 k w resistor in series with the status pin. a resistor for input protection is integrated. 3) r i = internal resistance of the load dump test pulse generator 4) v load dump is setup without the dut connected to the generator per iso 7637-1 and din 40839 5 ) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm 2 (one layer, 70 m m thick) copper area for v bb connection. pcb is vertical without blown air. see page 15 6 ) soldering point: upper side of solder edge of device pin 15. see page 15
bts 726 l1 semiconductor group 4 electrical characteristics parameter and conditions, each of the two channels symbol values unit at t j = 25 c, v bb = 12 v unless otherwise specified min typ max load switching capabilities and characteristics on-state resistance (v bb to out) i l = 2 a each channel, t j = 25c: t j = 150c: two parallel channels, t j = 25c: r on -- 50 100 25 60 120 30 m w nominal load current one channel active: two parallel channels active: device on pcb 5) , t a = 85c, t j 150c i l(nom) 3.6 5.5 4.0 6.0 -- a output current while gnd disconnected or pulled up; v bb = 30 v, v in = 0, see diagram page 9 i l(gndhigh) -- -- 10 ma turn-on time to 90% v out : turn-off time to 10% v out : r l = 12 w , t j =-40...+150c t on t off 80 80 200 230 400 450 m s slew rate on 10 to 30% v out , r l = 12 w , t j =-40...+150c: d v /dt on 0.1 -- 1 v/ m s slew rate off 70 to 40% v out , r l = 12 w , t j =-40...+150c: -d v /dt off 0.1 -- 1 v/ m s operating parameters operating voltage 7 ) t j =-40...+150c: v bb(on) 5.0 -- 34 v undervoltage shutdown t j =-40...+150c: v bb(under) 3.5 -- 5.0 v undervoltage restart t j =-40...+25c: t j =+150c: v bb(u rst) -- -- 5.0 7.0 v undervolta g e restart of char g e pump see diagram page 14 t j =-40...+150c: v bb(ucp) -- 5.6 7.0 v undervolta g e h y steresis d v bb(under) = v bb(u rst) - v bb(under) d v bb(under) -- 0.2 -- v overvoltage shutdown t j =-40...+150c: v bb(over) 34 -- 43 v overvoltage restart t j =-40...+150c: v bb(o rst) 33 -- -- v overvoltage hysteresis t j =-40...+150c: d v bb(over) -- 0.5 -- v overvoltage protection 8 ) t j =-40...+150c: i bb = 40 ma v bb(az) 42 47 -- v standby current, all channels off t j =25c : v in = 0 t j =150c: i bb(off) -- -- 20 29 50 56 m a 7) at supply voltage increase up to v bb = 5.6 v typ without charge pump, v out ? v bb - 2 v 8) see also v on(cl) in circuit diagram on page 8.
bts 726 l1 parameter and conditions, each of the two channels symbol values unit at t j = 25 c, v bb = 12 v unless otherwise specified min typ max semiconductor group 5 leakage output current (included in i bb ( off ) ) v in = 0 i l(off) -- -- 12 m a operating current 9) , v in = 5v, t j =-40...+150c i gnd = i gnd1 + i gnd2 , one channel on: two channels on: i gnd -- -- 1.8 3.6 3.5 7 ma protection functions initial peak short circuit current limit, (see timing diagrams, page 12) each channel, t j =-40c: t j =25c: t j =+150c: i l(scp) 21 15 11 32 25 17 43 35 24 a two parallel channels twice the current of one channel repetitive short circuit current limit, t j = t jt each channel two parallel channels (see timing diagrams, page 12) i l(scr) -- -- 16 16 -- -- a initial short circuit shutdown time t j,start =-40c: t j,start = 25c: (see page 11 and timing diagrams on page 12) t off(sc) -- -- 5 4 -- -- ms output clamp (inductive load switch off) 10) at v on(cl) = v bb - v out v on(cl) -- 47 -- v thermal overload trip temperature t jt 150 -- -- c thermal hysteresis d t jt -- 10 -- k reverse battery reverse battery voltage 11 ) - v bb -- -- 32 v drain-source diode volta g e (v out > v bb ) i l = - 4.0 a, t j = +150c - v on -- 610 -- mv 9 ) add i st , if i st > 0 10 ) if channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest v on(cl) 11 ) requires a 150 w resistor in gnd connection. the reverse load current through the intrinsic drain-source diode has to be limited by the connected load. note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. the temperature protection is not active during reverse current operation! input and status currents have to be limited (see max. ratings page 3 and circuit page 8).
bts 726 l1 parameter and conditions, each of the two channels symbol values unit at t j = 25 c, v bb = 12 v unless otherwise specified min typ max semiconductor group 6 diagnostic characteristics open load detection current, (on-condition) each channel, t j = -40c: t j = 25c: t j = 150c: i l (ol) 1 20 20 20 -- -- -- 850 750 750 ma two parallel channels twice the current of one channel open load detection voltage 12 ) t j =-40..+150c: v out(ol) 234v internal output pull down (out to gnd), v out = 5 v t j =-40..+150c: r o 41030k w input and status feedback 13 ) input resistance (see circuit page 8) t j =-40..+150c: r i 2.5 3.5 6 k w input turn-on threshold volta g e t j =-40..+150c: v in(t+) 1.7 -- 3.5 v input turn-off threshold volta g e t j =-40..+150c: v in(t-) 1.5 -- -- v input threshold hysteresis d v in(t) -- 0.5 -- v off state input current v in = 0.4 v: t j =-40..+150c: i in(off) 1--50 m a on state input current v in = 5 v: t j =-40..+150c: i in(on) 20 50 90 m a dela y time for status with open load after switch off (see timing diagrams, page 13 ), t j =-40..+150c: t d(st ol4) 100 520 1000 m s status invalid after positive input slope (open load) t j =-40..+150c: t d(st) -- 250 600 m s status output (open drain) zener limit voltage t j =-40...+150c, i st = +1.6 ma: st low voltage t j =-40...+25c, i st = +1.6 ma: t j = +150c, i st = +1.6 ma: v st(high) v st(low) 5.4 -- -- 6.1 -- -- -- 0.4 0.6 v 12) external pull up resistor required for open load detection in off state. 13) if ground resistors r gnd are used, add the voltage drop across these resistors.
bts 726 l1 semiconductor group 7 truth table cannel 1 input 1 output 1 status 1 cannel 2 input 2 output 2 status 2 level level bts 726l1 normal operation l h l h h h open load l h z h h (l 14 ) ) l short circuit to v bb l h h h l 15 ) h (l 16 ) ) overtem- perature l h l l h l under- voltage l h l l h h overvoltage l h l l h h l = "low" level x = don't care z = high impedance, potential depends on external circuit h = "high" level status signal valid after the time delay shown in the timing diagrams parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. the status outputs st1 and st2 have to be configured as a 'wired or' function with a single pull-up resistor. terms profet in1 st1 out1 gnd1 v bb v st1 v in1 i in1 v bb i l1 v out1 i gnd1 v on1 2 3 4 leadframe 17,18 i bb i st1 r gnd1 chip 1 profet in2 st2 out2 gnd2 v bb v st2 v in2 i in2 i l2 v out2 i gnd2 v on2 6 7 8 leadframe 13,14 i st2 r gnd2 chip 2 leadframe (v bb ) is connected to pin 1,10,11,12,15,16,19,20 external r gnd optional; two resistors r gnd1 , r gnd2 = 150 w or a single resistor r gnd = 75 w for reverse battery protection up to the max. operating voltage. 14 ) with external resistor between output and v bb 15) an external short of output to v bb in the off state causes an internal current from output to ground. if r gnd is used, an offset voltage at the gnd and st pins will occur and the v st low signal may be errorious. 16 ) low resistance to v bb may be detected by no-load-detection
bts 726 l1 semiconductor group 8 input circuit (esd protection), in1 or in2 in gnd i r esd-zd i i i esd zener diodes are not to be used as voltage clamp at dc conditions. operation in this mode may result in a drift of the zener voltage (increase of up to 1 v). status output, st1 or st2 st gnd esd- zd +5v r st(on) esd-zener diode: 6.1 v typ., max 5.0 ma; r st(on) < 380 w at 1.6 ma, esd zener diodes are not to be used as voltage clamp at dc conditions. operation in this mode may resul t in a drift of the zener voltage (increase of up to 1 v). inductive and overvoltage output clamp, out1 or out2 +v bb out profet v z v on power gnd v on clamped to v on(cl) = 47 v typ. overvoltage protection of logic part gnd1 or gnd2 + v bb in st st r gnd gnd r signal gnd logic profet v z2 i r v z1 v z1 = 6.1 v typ., v z2 = 47 v typ., r i = 3.5 k w typ. , r gnd = 150 w , r st = 15 k w nominal. reverse battery protection gnd logic st r in st + 5v out l r power gnd gnd r signal gnd power inverse i r v bb - diode r gnd = 150 w, r i = 3.5 k w typ , temperature protection is not active during inverse current operation.
bts 726 l1 semiconductor group 9 open-load detection, out1 or out2 on-state diagnostic condition: v on < r on i l(ol) ; in high open load detection logic unit + v bb out on v on off-state diagnostic condition: v out > 3 v typ.; in low open load detection logic unit v out signal gnd r ext r o off gnd disconnect profet v in st out gnd bb v bb v in v st v gnd any kind of load. in case of in = high is v out ? v in - v in(t+) . due to v gnd > 0, no v st = low signal available. gnd disconnect with gnd pull up profet v in st out gnd bb v bb v gnd v in v st any kind of load. if v gnd > v in - v in(t+) device stays off due to v gnd > 0, no v st = low signal available. v bb disconnect with energized inductive load profet v in st out gnd bb v bb high for an inductive load current up to the limit defined by e as (max. ratings see page 3 and diagram on page 10) each switch is protected against loss of v bb . consider at your pcb layout that in the case of vbb dis- connection with energized inductive load the whole load current flows through the gnd connection.
bts 726 l1 semiconductor group 10 inductive load switch-off energy dissipation profet v in st out gnd bb = e e e e as bb l r e load r l l { l z energy stored in load inductance: e l = 1 / 2 l i 2 l while demagnetizing load inductance, the energy dissipated in profet is e as = e bb + e l - e r = v on(cl) i l (t) dt, with an approximate solution for r l > 0 w : e as = i l l 2 r l ( v bb + |v out(cl) |) ln (1+ i l r l |v out(cl) | ) maximum allowable load inductance for a single switch off (one channel) 5) l = f (i l ); t j,start = 150c, v bb = 12 v, r l = 0 w l [mh] 1 10 100 1000 23456789101112 i l [a]
bts 726 l1 semiconductor group 11 typ. on-state resistance r on = f (v bb ,t j ) ; i l = 2 a, in = high r on [mohm] 0 25 50 75 100 125 150 0 10203040 t j = 150c 85c 25c -40 v bb [v] typ. open load detection current i l(ol) = f (v bb ,t j ); in = high i l(ol) [ma] 0 50 100 150 200 250 300 350 400 450 500 0102030 no load detection not specified for v bb < 6 v t j = 150c 85c 25c -40c v bb [v] typ. standby current i bb(off) = f (t j ) ; v bb = 9...34 v, in1,2 = low i bb(off) [ m a] 0 5 10 15 20 25 30 35 40 -50 0 50 100 150 200 t j [c] typ. initial short circuit shutdown time t off(sc) = f (t j,start ) ; v bb =12 v t off(sc) [msec] 0 1 2 3 4 5 6 -50 0 50 100 150 200 t j,start [c]
bts 726 l1 semiconductor group 12 figure 1a: v bb turn on: in2 v out1 t v bb st open drain in1 v out2 figure 2a: switching a lamp: in st out l t v i the initial peak current should be limited by the lamp and not by the initial short circuit current i l(scp) = 25 a typ. of the device. figure 2b: switching an inductive load in st l t v i *) out t d(st) i l(ol) *) if the time constant of load is too large, open-load-status may occur figure 3a: turn on into short circuit: shut down by overtemperature, restart by cooling other channel: normal operation t i st in1 l1 l(scr) i i l(scp) t off(sc) heating up of the chip may require several milliseconds, depending on external conditions (t off(sc) vs. t j,start see page 11) timing diagrams both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2
bts 726 l1 semiconductor group 13 figure 3b: turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2) t st1/2 in1/2 l1 l2 l(scr) i i l(scp) i + i t off(sc) st1 and st2 have to be configured as a 'wired or' function st1/2 with a single pull-up resistor. figure 4a: overtemperature: reset if t j < t jt in st out j t v t figure 5a: open load: detection in on-state, turn on/off to open load in st out l t v i open t d(st) t d(st ol4) the status delay time t d(stol4) allows to distinguish between the failure modes "open load in on-state" and "overtemperature". figure 5b: open load: detection in on-state, open load occurs in on-state in st out l t v i open normal normal t d(st ol1) t d(st ol2) t d(st ol1) = 20 m s typ., t d(st ol2) = 10 m s typ
bts 726 l1 semiconductor group 14 figure 5c: open load: detection in on- and off-state (with r ext ), turn on/off to open load in st out l t v i open t d(st) figure 6a: undervoltage: in v out t v bb st v v bb(under) bb(u rst) figure 6b: undervoltage restart of charge pump bb(under) v v bb(u rst) v bb(over) v bb(o rst) v bb(u cp) off-state on-state v on(cl) v bb v on off-state in = high, normal load conditions. charge pump starts at v bb(ucp) = 5.6 v typ. figure 7a: overvoltage: in v out t v bb st on(cl) v v bb(over) v bb(o rst)
bts 726 l1 semiconductor group 15 package and ordering code standard p-dso-20-9 ordering code bts726l1 Q67060-S7003-A2 all dimensions in millimetres 1) does not include plastic or metal protrusions of 0.15 max per side 2) does not include dambar protrusion of 0.05 max per side definition of soldering point with temperature t s : upper side of solder edge of device pin 15. pin 15 printed circuit board (fr4, 1.5mm thick, one layer 70 m m, 6cm 2 active heatsink area) as a reference for max. power dissipation p tot , nominal load current i l(nom) and thermal resistance r thja

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